Some Interrupts examples bellow.

References: [1] RM0008 Reference manual; [2] Cortex^TM-M3 Technical Reference Manual

- All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode.^[1]
- Default priority table Ref. [1], starting on page 197

External interrupt - PB11 pin from low to high

// CLOCK
// enable clock for PB-high pins and AFIO; 
// this is clear, we need to clock device before we can use it
RCC->APB2ENR |= RCC_APB2ENR_IOPBEN;
RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
	
// GPIO
// set PB11 as input - default state after reset
// Input with pull-up / pull-down
GPIOB->CRH |= GPIO_CRH_CNF11_1;

// External interrupt configuration register 
// Ref. [1]: page 191
// in this case: PB11 map to EXTI3
// aware: index in EXTICR starting from 0 - for EXTI3 index is 2
AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI11_PB;

// mask interupt from line 11
EXTI->IMR |= EXTI_IMR_MR11;
	
// enable interupt for rising edge (from 0 to 1) on line 11
EXTI->RTSR |= EXTI_RTSR_TR11;
	
// finaly enable interupt; Ref. [2] page 63. 
// EXTI lines are mapped as: 
// EXTI1 - EXTI1_IRQn
// EXTI2 - EXTI2_IRQn
// EXTI3 - EXTI3_IRQn
// EXTI4 - EXTI4_IRQn
// EXTI5-9 - EXTI9_5_IRQn   - shared for EXTI5-EXTI9
// EXTI10-15 - EXTI15_10_IRQn - shared for EXTI10-EXTI15
//
// - we can enable all interupts by: NVIC->ISER[0] = NVIC->ISER[1] = 0xFFFFFFFF;
// - one interupt with CMSIS: NVIC_EnableIRQ(EXTI15_10_IRQn);
// - or use this one, exactly the same as in CMSIS:
NVIC->ISER[((uint32_t)(EXTI15_10_IRQn) >> 5)] = (1 << ((uint32_t)(EXTI15_10_IRQn) & 0x1F));


// waiting for interrupt
while(1) {

}
	

void  EXTI15_10_IRQHandler (void)
{
	// As I mentioned before, EXTI15_10 is shared, so we need to test which line was genereated interrupt
	// and if interupt line is masked (not sure if this is really necessary)
	if ( (EXTI->PR & EXTI_PR_PR11) && (EXTI->IMR & EXTI_PR_PR11) )
	{
		// clear pending status
		EXTI->PR |= EXTI_PR_PR11;
			
		// do something...
		// ...
	}
}